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Version 2.2, 09 October 2007
CCM-PFC
ICE2PCS01 ICE2PCS01G
Standalone Power Factor Correction (PFC) Controller in Continuous Conduction Mode (CCM)
Pow e r M a na ge m e nt & S upply
Never
stop
thinking.
CCM-PFC Revision History: Previous Version: V 2.1 2007-10-09 Datasheet
Page
Subjects (major changes since last revision) Specifications in Supply Section changed GATE LOW Voltage changed Package outline dimension changed
14 17 18
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Edition 2007-10-09 Published by Infineon Technologies AG 81726 Munchen, Germany
(c) 2007 Infineon Technologies AG All Rights Reserved.
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CCM-PFC
Standalone Power Factor Correction (PFC) Controller in Continuous Conduction Mode (CCM)
Product Highlights
* * * * * * *
* * * * * * * * * * * * * * * *
ICE2PCS01 ICE2PCS01G
ICE2PCS01
PG-DIP-8
Leadfree DIP and DSO Package Wide Input Range Optimized for applications which require fast Startup Output Power Controllable by External Sense Resistor Programmable Operating Frequency Output Over-Voltage Protection Fast Output Dynamic Response during Load Jumps
ICE2PCS01G test
PG-DSO-8
Features
Ease of Use with Few External Components Supports Wide Range Average Current Control External Current and Voltage Loop Compensation for Greater User Flexibility Programmable Operating/Switching Frequency (50kHz - 250kHz) Max Duty Cycle of 95% (at 25C) at 125kHz Trimmed Internal Reference Voltage (3V+2% at 25C) VCC Under-Voltage Lockout Cycle by Cycle Peak Current Limiting Output Over-Voltage Protection Open Loop Detection Enhanced Dynamic Response Short Startup(SoftStart) duration Fulfills Class D Requirements of IEC 1000-3-2 Soft Overcurrent Protection
Description
The ICE2PCS01/G is a 8-pin wide input range controller IC for active power factor correction converters. It is designed for converters in boost topology, and requires few external components. Its power supply is recommended to be provided by an external auxiliary supply which will switch on and off the IC. The IC operates in the CCM with average current control, and in DCM only under light load condition. The switching frequency is programmable by the resistor at pin 4. Both compensations for the current and voltage loop are external to allow full user control. There are various protection features incorporated to ensure safe system operation conditions. The internal reference is trimmed (3V+2%) to ensure precise protection and control level. The device has a fast startup time with controlled peak start up current.
Typical Application
Auxiliary Supply
85 ... 265 VAC
VOUT
VCC
EMI-Filter
SWITCH PFC-Controller
ICE2PCS01/ ICE2PCS01G Protection Unit
GATE FREQ
PWM Logic Driver
Voltage Loop Compensation
VSENSE
Variable Oscillator Current Loop Compensation
ISENSE
Ramp Generator Nonlinear Gain
GND
VCOMP
ICOMP
Type ICE2PCS01 ICE2PCS01G
Version 2.2
Package PG-DIP-8 PG-DSO-8
3 09 October 2007
CCM-PFC ICE2PCS01/G
1 1.1 1.2 2 3 3.1 3.2 3.3 3.4 3.4.1 3.4.2 3.4.3 3.4.4 3.5 3.6 3.6.1 3.6.2 3.6.3 3.6.4 3.7 3.8 3.8.1 3.8.2 3.9 4 4.1 4.2 4.3 4.3.1 4.3.2 4.3.3 4.3.4 4.3.5 4.3.6 4.3.7 5 Pin Configuration and Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Pin Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Representative Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Start-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 System Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Soft Over Current Control (SOC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Peak Current Limit (PCL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Open Loop Protection / Input Under Voltage Protect (OLP) . . . . . . . . . . . 9 Over-Voltage Protection (OVP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Frequency Setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Average Current Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Complete Current Loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Current Loop Compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Pulse Width Modulation (PWM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Nonlinear Gain Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 PWM Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Voltage Loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Voltage Loop Compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Enhanced Dynamic Response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Output Gate Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Supply Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Variable Frequency Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 PWM Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 System Protection Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Current Loop Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Voltage Loop Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Driver Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Outline Dimension . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
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Pin Configuration and Functionality
1
1.1
Pin 1 2 3 4 5 6 7 8
Pin Configuration and Functionality
Pin Configuration
Symbol GND ICOMP ISENSE FREQ VCOMP Function IC Ground Current Loop Compensation Current Sense Input Switching Frequency Setting Voltage Loop Compensation ICOMP (Current Loop Compensation) Low pass filter and compensation of the current control loop. The capacitor which is connected at this pin integrates the output current of OTA2 and averages the current sense signal. ISENSE (Current Sense Input) The ISENSE Pin senses the voltage drop at the external sense resistor (R1). This is the input signal for the average current regulation in the current loop. It is also fed to the peak current limitation block. During power up time, high inrush currents cause high negative voltage drop at R1, driving currents out of pin 3 which could be beyond the absolute maximum ratings. Therefore a series resistor (R2) of around 220 is recommended in order to limit this current into the IC. FREQ (Frequency Setting) This pin allows the setting of the operating switching frequency by connecting a resistor to ground. The frequency range is from 50kHz to 250kHz. VSENSE (Voltage Sense/Feedback) The output bus voltage is sensed at this pin via a resistive divider. The reference voltage for this pin is 3V. VCOMP (Voltage Loop Compensation) This pin provides the compensation of the output voltage loop with a compensation network to ground (see Figure 2). This also gives the soft start function which controls an increasing AC input current during start-up. VCC (Power Supply) The VCC pin is the positive supply of the IC and should be connected to an external auxiliary supply. The operating range is between 11V and 26V. The turn-on threshold is at 11.8V and under voltage occurs at 11V. There is no internal clamp for a limitation of the power supply. GATE The GATE pin is the output of the internal driver stage, which has a capability of 1.5A instantaneous source and 2.0A instantaneous sink current. Its gate drive voltage is clamped at 15V (typically).
VSENSE VOUT Sense (Feedback) Input VCC GATE IC Supply Voltage Gate Drive Output
Package PG-DIP-8 / PG-DSO-8
GND
1
8
GATE
ICOMP
2
7
VCC
ISENSE
3
6
VSENSE
FREQ
4
5
VCOMP
Figure 1
Pin Configuration (top view)
1.2
Pin Functionality
GND (Ground) The ground potential of the IC.
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Figure 2
D2 ... D5 D6 L1 D1 R3 Vout C2 R4 R1 auxiliary supply R2 R7 C1
Version 2.2
GND VCC GATE
PWM Logic
OSC CLK R S
RFI Filter
Vin 85 ... 265 VAC
ICE2PCS01/G
Gate Driver
Variable Oscillator
FREQ
2.5%T
1.7V
Representative Block diagram
Toff min R S
OTA3
R5 Protection Block
UVLO VCC
Peak Current Limit Ramp Generator
300ns PWM Comparator
C1
Over-current Comparator C4
undervoltage lockout Protection Logic 3.25V
Representative Block diagram
6
Deglitcher PowerDown C3
1.5V
C2
OverVoltage protect
VSENSE
0.6V open-loop protect
ISENSE
Current Sense Opamp
-1.43x
OP1
VCOMP
Current Loop
Voltage Loop
0.75 V
0
R6
+/-30A, 39S OTA1
ICOMP
Nonlinear Gain
Current Loop Compensation
C4
-ve
C5
3V Soft Over Current Control 2.85V
+ve 0 -ve
OTA2
C3
1.0mS +/-50A linear range
3.18V
S2
4.2V
Fault
Representative Block diagram
CCM-PFC ICE2PCS01/G
09 October 2007
Fault
Window Detect
S1
CCM-PFC ICE2PCS01/G
3
3.1
Functional Description
General
Functional Description
The ICE2PCS01/G is a 8 pin control IC for power factor correction converters. It comes in both DIP and DSO packages and is suitable for wide range line input applications from 85 to 265 VAC. The IC supports converters in boost topology and it operates in continuous conduction mode (CCM) with average current control. The IC operates with a cascaded control; the inner current loop and the outer voltage loop. The inner current loop of the IC controls the sinusoidal profile for the average input current. It uses the dependency of the PWM duty cycle on the line input voltage to determine the corresponding input current. This means the average input current follows the input voltage as long as the device operates in CCM. Under light load condition, depending on the choke inductance, the system may enter into discontinuous conduction mode (DCM). In DCM, the average current waveform will be distorted but the resultant harmonics are still low enough to meet the Class D requirement of IEC 10003-2. The outer voltage loop controls the output bus voltage. Depending on the load condition, OTA1 establishes an appropriate voltage at VCOMP pin which controls the amplitude of the average input current. The IC is equipped with various protection features to ensure safe operating condition for both the system and device. Important protection features are namely Open-Loop protection, Current Limitation and Output Over-voltage Protection.
If VCC drops below 11V, the IC is off. The IC will then be consuming typically 300A, whereas consuming 13mA during normal operation. The IC can be turned off and forced into standby mode by pulling down the voltage at pin 6 (VSENSE) to lower than 0.6V. The current consumption is reduced to 300A in this mode.
3.3
Start-up
Figure 4 shows the operation of voltage loop's OTA1 during startup. The VCOMP pin is pull internally to ground via switch S1 during UVLO and other fault conditions (see later section on "System Protection"). During power up when VOUT is less than 83% of the rated level, OTA1 sources an output current, maximum 30A, into the compensation network at pin 5 (VCOMP) causing the voltage at this pin to rise linearly. This results in a controlled linear increase of the input current from 0A thus reducing the stress on the external component.
VSENSE
( R4 x V OUT ) R3 + R4
OTA1
VCOMP
S1
3V p ro te c t
3.2
Power Supply
R6 C4 C5
An internal under voltage lockout (UVLO) block monitors the VCC power supply. As soon as it exceeds 11.8V and the voltage at pin 6 (VSENSE) is >0.6V, the IC begins operating its gate drive and performs its Startup as shown in Figure 3. .
(VVSENSE > 0.6 V) (VVSENSE < 0.6 V) (VVSENSE > 0.6 V)
IC E 2 P C S 0 1 /G
Figure 4
Startup Circuit
VCC 11.8 V 11.0 V
As VOUT has not reached within 5% from the rated value, VCOMP voltage is level-shifted by the window detect block as shown in Figure 5, to ensure there is fast boost up of the output voltage. When VOUT approaches its rated value, OTA1's sourcing current drops and the level shift of the window detect block is removed. The normal voltage loop then takes control.
t IC's Start Normal Open loop/ OFF Up Operation Standby State
Figure 3
Normal Operation OFF
State of Operation respect to VCC
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Functional Description 3.4
Window Detect
Max Vcomp current
System Protection
Normal Control VOUT =rated
VOUT
The IC provides several protection features in order to ensure the PFC system in safe operating range. Depending on the input line voltage (VIN) and output bus voltage (VOUT), Figure 7 and 8 show the conditions when these protections are active.
VCC > VCCUVLO VCC95%rated 83%rated
t
av(IIN)
Level-shifted VCOMP
VIN (VAC)
VCOMP
IC's State
Normal Operation
t
IC OFF
t
Figure 5 Startup with controlled maximum current
Figure 6
VIN Related Protection Features
108% 100%
VOUT VOUT,Rated
20%
t
PCL / SOC OLP OVP OLP
Figure 7
VOUT Related Protection Features
The following sections describe the functionality of these protection features.
3.4.1 Soft Over Current Control (SOC) The IC is designed not to support any output power that corresponds to a voltage lower than -0.75V at the ISENSE pin. A further increase in the inductor current, which results in a lower ISENSE voltage, will activate the Soft Over Current Control (SOC). This is a soft control as it does not directly switch off the gate drive. It acts on the nonlinear gain block to result in a reduced PWM duty cycle.
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Functional Description
connected) or an insufficient input voltage VIN for normal operation. In this case, most of the blocks within the IC will be shutdown. It is implemented using comparator C3 with a threshold of 0.6V as shown in the IC block diagram in Figure 2. 3.4.4 Over-Voltage Protection (OVP) Whenever VOUT exceeds the rated value by 5%, the over-voltage protection OVP is active as shown in Figure 6. This is implemented by sensing the voltage at pin VSENSE with respect to a reference voltage of 3.15V. A VSENSE voltage higher than 3.15V will immediately reduce the output duty cycle, bypassing the normal voltage loop control. This results in a lower input power to reduce the output voltage VOUT. A VSENSE voltage higher than 3.25V will immediately turn off the gate, thereby preventing damage to bus capacitor.
POUT(rated)
POUT(max)
IC's State
Normal Operation
SOC
PCL
VISENSE
0
-0.61V -0.75V
-1.04V
Figure 8
SOC and PCL Protection as function of VISENSE
The rated output power with a minimum VIN (VINMIN) is 0.61 P OUT ( rated ) = V INMIN x -----------------R1 2 Due to the internal parameter tolerance, the maximum power with VINMIN is 0.75 P OUT ( max ) = V INMIN x -----------------R1 2 3.4.2 Peak Current Limit (PCL) The IC provides a cycle by cycle peak current limitation (PCL). It is active when the voltage at pin 3 (ISENSE) reaches -1.04V. This voltage is amplified by OP1 by a factor of -1.43 and connected to comparator C2 with a reference voltage of 1.5V as shown in Figure 9. A deglitcher with 300ns after the comparator improves noise immunity to the activation of this protection.
Full-wave Rectifier Current Limit 1.5V
C 2
3.5
Frequency Setting
The switching frequency of the PFC converter can be set with an external resistor R5 at FREQ pin as shown Figure 10. The pin voltage VFREQ is typically 1.7V. The corresponding capacitor for the oscillator is integrated in the device and the R5/frequency relationship is given at the "Electrical Characteristic" section. The recommended operating frequency range is from 50kHz to 250kHz. As an example, a R5 of 33k at pin FREQ will set a switching frequency FSW of 136kHz typically.
Deglitcher
300ns
ISENSE
R2 1.43x IINDUCTOR R1
O1 P
Turn Off Driver
ICE2PCS01/G
Figure 9 3.4.3 Peak Current Limit (PCL)
Open Loop Protection / Input Under Voltage Protect (OLP) Whenever VSENSE voltage falls below 0.6V, or equivalently VOUT falls below 20% of its rated value, it indicates an open loop condition (i.e. VSENSE pin not
Figure 10
Frequency Versus RFREQ
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Functional Description 3.6 Average Current Control
From the above equation, DOFF is proportional to VIN. The objective of the current loop is to regulate the average inductor current such that it is proportional to the off duty cycle DOFF, and thus to the input voltage VIN. Figure 12 shows the scheme to achieve the objective.
ramp profile
3.6.1 Complete Current Loop The complete system current loop is shown in Figure 11.
L1 R7 D1 C2 R4 R2 R1 Vout
From Full-wave Retifier
R3
ave(IIN) at ICOMP
GATE ISENSE
Current Loop
voltage proportional to averaged Inductor current
Gate Driver
ICOMP
Current Loop Compensation OTA2 1.0mS +/-50uA (linear range) S2 4.2V Fault
PWM Comparator
C1
RQ S
GATE drive
PWM Logic Nonlinear Gain
Input From Voltage Loop
C3
t
Figure 12 Average Current Control in CCM The PWM is performed by the intersection of a ramp signal with the averaged inductor current at pin 5 (ICOMP). The PWM cycle starts with the Gate turn off for a duration of TOFFMIN (250ns typ.) and the ramp is kept discharged. The ramp is then allowed to rise after TOFFMIN expires. The off time of the boost transistor ends at the intersection of the ramp signal and the averaged current waveform. This results in the proportional relationship between the average current and the off duty cycle DOFF. Figure 13 shows the timing diagrams of TOFFMIN and the PWM waveforms.
2.5% of T TOFFMIN PWM cycle
ICE2PCS01/G
Figure 11
Complete System Current Loop
It consists of the current loop block which averages the voltage at pin ISENSE, resulted from the inductor current flowing across R1. The averaged waveform is compared with an internal ramp in the ramp generator and PWM block. Once the ramp crosses the average waveform, the comparator C1 turns on the driver stage through the PWM logic block. The Nonlinear Gain block defines the amplitude of the inductor current. The following sections describe the functionality of each individual blocks. 3.6.2 Current Loop Compensation The compensation of the current loop is done at the ICOMP pin. This is the OTA2 output and a capacitor C3 has to be installed at this node to ground (see Figure 11). Under normal mode of operation, this pin gives a voltage which is proportional to the averaged inductor current. This pin is internally shorted to 4.2V in the event of IC shuts down when OLP and UVLO occur. 3.6.3 Pulse Width Modulation (PWM) The IC employs an average current control scheme in continuous conduction mode (CCM) to achieve the power factor correction. Assuming the voltage loop is working and output voltage is kept constant, the off duty cycle DOFF for a CCM PFC system is given as V IN D OFF = ------------V OUT
VCREF(1) VRAMP PWM ramp released
t
(1)
VCREF is a function of VICOMP
Figure 13
Ramp and PWM waveforms
3.6.4 Nonlinear Gain Block The nonlinear gain block controls the amplitude of the regulated inductor current. The input of this block is the
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Functional Description
voltage at pin VCOMP. This block has been designed to support the wide input voltage range (85-265VAC).
3.7
PWM Logic
From Full-wave Retifier
L1 R7
D1 C2
R3
Vout
The PWM logic block prioritizes the control input signals and generates the final logic signal to turn on the driver stage. The speed of the logic gates in this block, together with the width of the reset pulse TOFFMIN, are designed to meet a maximum duty cycle DMAX of 95% at the GATE output under 136kHz of operation. In case of high input currents which result in Peak Current Limitation, the GATE will be turned off immediately and maintained in off state for the current PWM cycle. The signal Toffmin resets (highest priority, overriding other input signals) both the current limit latch and the PWM on latch as illustrated in Figure 14.
R4
Current Loop + PWM Generation VIN
Nonlinear Gain
Gate Driver
GATE
OTA1
Av(IIN)
3V
t
VSENSE
Peak Current Limit
Current Limit Latch Q S L1 R PWM on Latch S L2 R Q
ICE2PCS01/G
G1 HIGH = turn GATE on
VCOMP
R6 C4 C5
Current Loop PWM on signal Toffmin 2.5% of T
Figure 15
Voltage Loop
Figure 14
PWM Logic
3.8
Voltage Loop
The voltage loop is the outer loop of the cascaded control scheme which controls the PFC output bus voltage VOUT. This loop is closed by the feedback sensing voltage at VSENSE which is a resistive divider tapping from VOUT. The pin VSENSE is the input of OTA1 which has an internal reference of 3V. Figure 15 shows the important blocks of this voltage loop. 3.8.1 Voltage Loop Compensation The compensation of the voltage loop is installed at the VCOMP pin (see Figure 15). This is the output of OTA1 and the compensation must be connected at this pin to ground. The compensation is also responsible for the soft start function which controls an increasing AC input current during start-up.
3.8.2 Enhanced Dynamic Response Due to the low frequency bandwidth of the voltage loop, the dynamic response is slow and in the range of about several 10ms. This may cause additional stress to the bus capacitor and the switching transistor of the PFC in the event of heavy load changes. The IC provides therefore a "window detector" for the feedback voltage VVSENSE at pin 6 (VSENSE). Whenever VVSENSE exceeds the reference value (3V) by +5%, it will act on the nonlinear gain block which in turn affect the gate drive duty cycle directly. This change in duty cycle is bypassing the slow changing VCOMP voltage, thus results in a fast dynamic response of VOUT.
3.9
Output Gate Driver
The output gate driver is a fast totem pole gate drive. It has an in-built cross conduction currents protection and a Zener diode Z1 (see Figure 16) to protect the external transistor switch against undesirable over voltages. The maximum voltage at pin 8 (GATE) is typically clamped at 15V. The output is active HIGH and at VCC voltages below the under voltage lockout threshold VCCUVLO, the gate drive is internally pull low to maintain the off state.
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Functional Description
VCC
PWM Logic HIGH to turn on
Gate Driver
LV Z1
External MOS
GATE
* LV: Level Shift
ICE2PCS01/G
Figure 16 Gate Driver
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Electrical Characteristics
4
4.1
Note:
Electrical Characteristics
Absolute Maximum Ratings
Absolute maximum ratings are defined as ratings, which when being exceeded may lead to destruction of the integrated circuit. Symbol VCC VFREQ VICOMP VISENSE IISENSE VVSENSE IVSENSE VVCOMP VGATE Tj TS RthJA (DSO) RthJA(DIP) VESD Limit Values min. max. 25 5 5 5 1 5 1 5 17 150 150 185 90 2 V V V V mA V mA V V C C K/W K/W kV PG-DSO-8-13 PG-DIP-8-4 Human Body Model1) Clamped at 15V if driven internally. R3>400k
2)
Parameter VCC Supply Voltage FREQ Voltage ICOMP Voltage ISENSE Voltage ISENSE Current VSENSE Voltage VSENSE Current VCOMP Voltage GATE Voltage Junction Temperature Storage Temperature Thermal Resistance Junction-Ambient for DSO-8-13 Thermal Resistance Junction-Ambient for DIP-8-4 ESD Protection
1) 2)
Unit
Remarks
-0.3 -0.3 -0.3 -20 -1 -0.3 -1 -0.3 -0.3 -40 -55 -
Recommended R2=220
According to EIA/JESD22-A114-B (discharging a 100pF capacitor through a 1.5k series resistor) Absolute ISENSE current should not be exceeded
4.2
Note:
Operating Range
Within the operating range the IC operates as described in the functional description.
Parameter VCC Supply Voltage Junction Temperature
Symbol VCC TJCon
Limit Values min. -40 max. VCCUVLO 25 125
Unit V C
Remarks
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Electrical Characteristics 4.3
Note:
Characteristics
The electrical characteristics involve the spread of values within the specified supply voltage and junction temperature range TJ from - 40 C to 125C.Typical values represent the median values, which are related to 25C. If not otherwise stated, a supply voltage of VCC =18V is assumed for test condition.
4.3.1
Supply Section Symbol min. VCCon VCCUVLO VCChy ICCstart ICCHG ICCStdby Limit Values typ. 11.8 11.0 0.8 450 15 700 max. 12.7 11.7 1.4 1100 20 1300 V V V A mA A VVCC=VVCCon -0.1V R5 = 33k CL= 4.7nF VVSENSE= 0.5V VICOMP= 4V 11.4 10.4 0.65 Unit Test Condition
Parameter VCC Turn-On Threshold VCC Turn-Off Threshold/ Under Voltage Lock Out VCC Turn-On/Off Hysteresis Start Up Current Before VCCon Operating Current with active GATE Operating Current during Standby
4.3.2
Variable Frequency Section Symbol min. FSWnom FSWmin FSWmax VFREQ Limit Values typ. 136 56 285 1.70 max. 147 62 315 1.76 kHz kHz kHz V R5 = 33k R5 = 82k R5 = 15k 124 50 250 1.65 Unit Test Condition
Parameter Switching Frequency (Typical) Switching Frequency (Min.) Switching Frequency (Max.) Voltage at FREQ pin
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Electrical Characteristics
4.3.3 PWM Section Symbol min. Max. Duty Cycle Min. Duty Cycle Min. Off Time DMAX DMIN TOFFMIN 100 250 92 Limit Values typ. 95 max. 98.5 0 580 % % ns FSW = FSWnom (R5 = 33k) VVCOMP= 0V, VVSENSE= 3V VICOMP= 4.3V VVSENSE= 3V VISENSE= 0.1V (R5 = 33k) Unit Test Condition Parameter
The parameter is not subject to production test - verified by design/characterization 4.3.4 System Protection Section Symbol min. Open Loop Protection (OLP) VSENSE Threshold Peak Current Limitation (PCL) ISENSE Threshold Soft Over Current Control (SOC) ISENSE Threshold Output Over-Voltage Protection (OVP) VOLP VPCL VSOC VOVP 0.55 -1.16 -0.75 3.1 Limit Values typ. 0.6 -1.04 -0.68 3.25 max. 0.65 -0.95 -0.61 3.4 V V V V Unit Test Condition
Parameter
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4.3.5 Current Loop Section Symbol min. OTA2 Transconductance Gain OTA2 Output Linear Range1) ICOMP Voltage during OLP GmOTA2 IOTA2 VICOMPF 0.8 3.9 Limit Values typ. 1.0 50 4.2 max. 1.3 mS A V VVSENSE= 0.5V At Temp = 25C Unit Test Condition
Parameter
4.3.6
Voltage Loop Section Symbol min. VOTA1 GmOTA1 IOTA1SO IOTA1SK Limit Values typ. 3.00 39 30 30 max. 3.08 51 38 41 V S A A VVSENSE= 2V VVCOMP= 3V VVSENSE= 4V VVCOMP= 3V measured at VSENSE 2.92 26 18 21 Unit Test Condition
Parameter OTA1 Reference Voltage OTA1 Transconductance Gain OTA1 Max. Source Current Under Normal Operation OTA1 Max. Sink Current Under Normal Operation Enhanced Dynamic Response VSENSE High Threshold VSENSE Low Threshold VSENSE Input Bias Current at 3V VSENSE Input Bias Current at 1V VCOMP Voltage during OLP
VHi VLo IVSEN3V IVSEN1V VVCOMPF
3.09 2.76 0 0 0
3.18 2.85 0.2
3.26 2.94 1.5 1 0.4
V V A A V VVSENSE= 3V VVSENSE= 1V VVSENSE= 0.5V IVCOMP= 0.5mA
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4.3.7 Driver Section Symbol VGATEL -0.2 GATE High Voltage VGATEH 7.8 GATE Rise Time GATE Fall Time GATE Current, Peak, Rising Edge GATE Current, Peak, Falling Edge
1)
Parameter GATE Low Voltage
Limit Values min. typ. max. 1.2 1.5 0.4 0 14.8 14.8 9.2 60 50 2.0 1.0 -
Unit Test Condition V V V V V V V V ns ns A A VCC =10V IGATE = 5 mA VCC =10V IGATE =20 mA IGATE = 0 A IGATE = 20 mA IGATE = -20 mA VCC = 25V CL = 4.7nF VCC = 19V CL = 4.7nF VCC = VVCCoff + 0.2V CL = 4.7nF VGate = 2V ...12V CL = 4.7nF VGate = 12V ...2V CL = 4.7nF CL = 4.7nF1) CL = 4.7nF1)
tr tf IGATE IGATE
-1.5 -
Design characteristics (not meant for production testing)
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Outline Dimension
5
Outline Dimension
Figure 17
PG-DSO-8 and PG-DIP-8 Outline Dimension
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